1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly relates to a semiconductor device provided with field-effect transistors of a complementary type and a method of manufacturing the same.
2. Description of the Background Art
A static semiconductor memory device, which will be referred to as a "Static Random Access Memory (SRAM)" hereinafter, has been known as a kind of semiconductor device. A memory cell in the SRAM is generally formed of a flip-flop circuit and transistors for reading and writing data. The SRAM is a semiconductor memory device which holds data in accordance with an operation situation of the flip-flop circuit. Such an SRAM has been known that uses field-effect transistors as load elements in the flip-flop circuit forming the memory cell.
FIG. 29 is an equivalent circuit diagram of a memory cell in an SRAM using field-effect transistors as load elements in the prior art. Referring to FIG. 29, the memory cell in the SRAM which uses field-effect transistors as load elements includes six transistors, i.e., access transistors A1 and A2, driver transistors D1 and D2, and load transistors T1 and T2. Driver transistors D1 and D2 and load transistors T1 and T2 form flip-flop circuits. Access transistors A1 and A2 are transistors for reading and writing data. Access transistors A1 and A2 and driver transistors D1 and D2 are n-type field-effect transistors. Load transistors T1 and T2 are p-type field-effect transistors. Therefore, driver transistors D1 and D2 and load transistors T1 and T2 form field-effect transistors of a complementary type. Access transistors A1 and A2 each have source/drain regions, one of which is connected to a bit line 117 or a complementary bit line 118. Gate electrodes of access transistors A1 and A2 are connected to a word line 113. Source regions of load transistors T1 and T2 are connected to a power supply line 114. Source regions of driver transistors D1 and D2 are connected to a ground line (not shown).
FIG. 30 is a layout plan showing a memory cell pattern of the SRAM using the field-effect transistors as the load transistors in the prior art. FIG. 31 is a cross section showing a structure taken along line 100--100 in FIG. 30.
Referring to FIGS. 30 and 31, description will now be given on the SRAM using the field-effect transistors as the load transistors in the prior art.
Referring to FIG. 30, the memory cell in the conventional SRAM which uses the field-effect transistors as the load transistors includes access transistors A1 and A2, driver transistors D1 and D2, load transistors T1 and T2, power supply line 114, ground lines 115 and 116, bit line 117, complementary bit line 118 and word line 113 also serving as gate electrodes of access transistors A1 and A2. Access transistor A1 includes gate electrode 113 and source/drain regions 111c and 111b. Access transistor A2 includes gate electrode 113 and source/drain regions 112c and 112b. Driver transistor D1 includes a gate electrode 107, a source regions 111a and a drain region 111b. Driver transistor D2 includes a gate electrode 108, a source region 112a and a drain region 112b. Load transistor T1 includes gate electrode 107, a source region 105a and a drain region 105b. Load transistor T2 includes gate electrode 108, a source region 106a and a drain region 106b. Source/drain regions 111a-111c and 112a-112c of access transistors A1 and A2 and driver transistors D1 and D2 are formed by implanting n-type impurity into a main surface of a semiconductor substrate. Source/drain regions 105a, 105b, 106a and 106b of load transistors T1 and T2 are formed by implanting p-type impurity into the main surface of the semiconductor substrate. Diffusion regions 103 and 104 of n-type impurity are formed at the main surface of the semiconductor substrate.
Gate electrodes 113, 107 and 108 of transistors A1, A2, D1, D2, T1 and T2 are formed of polycrystalline silicon films formed on the semiconductor substrate. Interconnections made of aluminum, i.e., internal interconnections 109 and 110, ground lines 115 and 116, power supply interconnections 140 and 141, and power supply line 114 are form at regions above these transistors with a first interlayer insulating film 142 (see FIG. 31) therebetween, respectively. Internal interconnection 109 is connected to drain region 105b of load transistor T1, gate electrodes 108 of load transistor T2 and driver transistor D2, and region 111b, i.e., one of the source/drain regions of access transistor A1 which also serves as the drain region of driver transistor D1, through contact holes 125, 127 and 129, respectively. Likewise, internal interconnection 110 is connected to drain region 106b of load transistor T2, gate electrodes 107 of load transistor T1 and driver transistor D1, and region 112b, i.e., one of the source/drain regions of access transistor A2 which also serves as the drain region of driver transistor D2, through contact holes 126, 128 and 130, respectively. Ground lines 115 and 116 are connected to source regions 111a and 112a of driver transistors D1 and D2 through contact holes 131 and 132, respectively. Power supply line 114 is in contact with n-type impurity diffusion regions 101 and 102 through contact holes 119 and 120, respectively. Power supply interconnection 140 is in contact with n-type impurity diffusion region 103 and source region 105a of load transistor T1 through contact holes 121 and 122, respectively. Power supply interconnection 141 is in contact with n-type impurity diffusion region 104 and source region 106a of load transistor T2 through contact holes 123 and 124, respectively.
A second interlayer insulating film 143 (FIG. 31) is formed over first interlayer insulating film 142, internal interconnections 109 and 110, ground lines 115 and 116, power supply interconnections 140 and 141, and power supply line 114. Bit line 117 and complementary bit line 118 are formed on second interlayer insulating film 143. The other source/drain region 111c and 112c of access transistors A1 and A2 are connected to bit line 117 and complementary bit line 118 through contact holes 133 and 134, respectively.
Referring to FIG. 31, n- and p-type wells 138 and 139 are formed at the main surface of semiconductor substrate 137. n-type impurity diffusion regions 101 and 103 and p-type impurity diffusion region 105a, i.e., a source region of load transistor T1 (FIG. 30) are formed at the main surface of n-type well 138. n-type diffusion region 111a, i.e., the source region of driver transistor D1 (FIG. 30) is formed at the main surface of p-type well 139. An isolating oxide film 135 is formed at the main surface of semiconductor substrate 137 between source region 105a of load transistor T1 and source region 111a of driver transistor D1. Interlayer insulating film 142 is formed over the main surface of semiconductor substrate 137 and isolating oxide film 135. Contact holes 119, 121, 122 and 131 are formed at regions above n-type impurity diffusion regions 101 and 103, source region 105a of load transistor T1 and source region 111a of driver transistor D1 by removing interlayer insulating film 142 from these regions. Power supply line 114 which is in contact with n-type impurity diffusion region 101 is formed in contact hole 119 and on interlayer insulating film 142. Power supply interconnection 140 made of aluminum is formed in contact holes 121 and 122 and on interlayer insulating film 142, and is in contact with n-type impurity diffusion region 103 and source region 105a of load transistor T1. Ground line 115 which is in contact with source region 111a of driver transistor D1 is formed in contact hole 131 and on interlayer insulating film 142.
In the memory cell of conventional SRAM, two bipolar transistors are parasitically formed as shown in FIG. 32. More specifically, there are formed a pnp bipolar transistor Q1 which includes an emitter electrode formed of source region 105a of load transistor T1, a base electrode formed of n-type well 138 and a collector electrode formed of p-type well 139 as well as a npn bipolar transistor Q2 which includes a collector electrode formed of n-type well 138, a base electrode formed of p-type well 139 and an emitter electrode formed of source region 111a of driver transistor D1. These parasitically formed bipolar transistors Q1 and Q2 parasitically form a thyristor. FIG. 32 is an equivalent circuit diagram of the thyristor which is parasitically formed in the conventional SRAM. Since the thyristor is parasitically formed, this thyristor may operate due to noises on the power supply voltage supplied to power supply line 114 (FIG. 31). When the parasitically formed thyristor operates, a current continuously flows from power supply line 114 to ground line 115 (FIG. 31). This phenomenon is called latch up. The latch up may impede the operation of the semiconductor element, and further may break the semiconductor element dues to heat generation by a large current.
As measures for the latch up in the prior art, n-type well 138 in FIG. 31 is used as a part of a path for supplying a power from power supply line 114 to source region 105a of load transistor T1. More specifically, a power supply current which is supplied to the power supply line 114 is transmitted from n-type impurity diffusion region 101 to n-type impurity diffusion region 103 through n-type well 138. Since the power supply current is transmitted from n-type impurity diffusion region 103 to source region 105a of load transistor T1 through power supply interconnection 140. Therefore, a substrate resistance of n-type well 138 can lower the power supply voltage supplied to source region 105a of load transistor T1, which is the emitter electrode of parasitically formed bipolar transistor Q1 (FIG. 32). As a result, the power supply current is supplied to the emitter electrode, i.e., source region 105a of load transistor T1 and n-type well 138, i.e., a base electrode of bipolar transistor Q1. Therefore, it is possible to prevent occurrence of forward bias between the emitter and base electrodes of bipolar transistor Q1. In this manner, the latch up is prevented in the prior art.
Demands for subminiaturization and increase in integration density of semiconductor devices are now increasing. In the conventional SRAM shown in FIG. 31, a space of at least about 5 .mu.m is kept between source region 105a of load transistor T1 and source region 111a of driver transistor D1, and isolating oxide film 135 has a length L of about 5 .mu.m. In view of the foregoing demands, it is now requested in some cases to reduce these space and length to a higher extent for subminiaturizing the memory cells. However, if the distance between the source region 105a of load transistor T1 and source region 111a of driver transistor D1 were further reduced below 5 .mu.m, the performance of parasitically formed bipolar transistors Q1 and Q2 would consequently be improved so that the latch up would be cause even by noises on the power supply voltage which are smaller than those in the prior art. Accordingly, it is difficult to achieve the subminiaturization of semiconductor elements and the increase in integration density only by the conventional measures utilizing a substrate resistance of n-type well 138, while preventing the latch up.